Conventionally, semiconductor memories such as static random access memory (“SRAM”) and dynamic random access memory (“DRAM”) are in widespread use. DRAM is very common due to its high density with a cell size typically between 6F2 and 8F2, where F is a minimum feature size. However, DRAM is relatively slow having access and cycle times commonly near 20 nanoseconds (“ns”). SRAM access and cycle times are typically an order of magnitude faster than DRAM. One of the reasons is that the typical SRAM bit cell provides data and inverse data outputs to be read. However, an SRAM cell is commonly made of four transistors and two resistors or of six transistors, thus leading to a density of approximately 60F2 to 100F2.
SRAM memory designs based on a negative differential resistance (“NDR”) cell, such as a thyristor cell, have been introduced to minimize the size of a conventional SRAM memory. In an array of thyristor-based memory cells, a Thin Capacitive Coupled Thyristor Cell (“TCCT”) bit cell has cross-coupled gain within the bit cell but the output is single-ended. Accordingly, coupling such single-ended bit cells to a common bitline may suffer from significant signal attenuation during an access operation of one such bit cell due to state of one or more adjacent bit cells. More particularly, with spacing between bitlines becoming smaller with successive microlithography reductions, capacitive coupling to adjacent bitlines may account for as much as half the total parasitic capacitive load of a bitline. If adjacent bitlines to a bitline being read are both at or moving in an opposite voltage direction to the bitline being read, signal attenuation on the bitline being read could cause significant delay in the time it takes to sample the bitline being read. Additional details regarding a thyristor-based memory cell may be found in Patent Cooperation Treaty (“PCT”) International Publication WO 02/082504.
Accordingly, it would be desirable and useful to provide means as part of a bit cell access operation to reduce data dependent cross talk from one or more adjacent bit cells.